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RM0008
6.3.9
Note:
Low-, medium- and high-density reset and clock control (RCC)
Bit 4 TIM6EN: Timer 6 clock enable
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
Bit 3 TIM5EN: Timer 5 clock enable
Set and cleared by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled
Bit 2 TIM4EN: Timer 4 clock enable
Set and cleared by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Bit 1 TIM3EN: Timer 3 clock enable
Set and cleared by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Bit 0 TIM2EN: Timer 2 clock enable
Set and cleared by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
Backup domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0 ? wait state ? 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-
protected and the DBP bit in the Power control register (PWR_CR) has to be set before
these can be modified. Refer to Section 5 on page 66 for further information. These bits are
only reset after a Backup domain Reset (see Section 6.1.3: Backup domain reset ). Any
internal or external Reset will not have any effect on these bits.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BDRST
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTC
EN
rw
Reserved
RTCSEL[1:0]
rw
rw
Reserved
LSE
BYP
rw
LSE
RDY
r
LSEON
rw
Bits 31:17
Reserved, always read as 0.
Doc ID 13902 Rev 9
99/995
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